NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 6

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6
5.11
5.12
5.13
Real Time Clock (D31:F0) ................................................................................. 152
5.11.1 Update Cycles ...................................................................................... 152
5.11.2 Interrupts ............................................................................................ 153
5.11.3 Lockable RAM Ranges............................................................................ 153
5.11.4 Century Rollover................................................................................... 153
5.11.5 Clearing Battery-Backed RTC RAM........................................................... 153
Processor Interface (D31:F0) ............................................................................ 155
5.12.1 Processor Interface Signals .................................................................... 155
5.12.2 Dual-Processor Issues (Desktop Only) ..................................................... 158
Power Management (D31:F0) ............................................................................ 159
5.13.1 Features .............................................................................................. 159
5.13.2 Intel
5.13.3 System Power Planes ............................................................................ 162
5.13.4 SMI#/SCI Generation ............................................................................ 162
5.13.5 Dynamic Processor Clock Control ............................................................ 165
5.13.6 Dynamic PCI Clock Control (Mobile Only) ................................................. 168
5.13.7 Sleep States ........................................................................................ 169
5.13.8 Thermal Management............................................................................ 173
5.13.9 Event Input Signals and Their Usage ....................................................... 174
5.12.1.1 A20M# (Mask A20).................................................................. 155
5.12.1.2 INIT# (Initialization)................................................................ 156
5.12.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore
5.12.1.4 NMI (Non-Maskable Interrupt) .................................................. 157
5.12.1.5 Stop Clock Request and CPU Sleep
5.12.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 157
5.12.1.7 Deeper Sleep (DPSLP#) (Mobile Only)........................................ 158
5.12.2.1 Signal Differences ................................................................... 158
5.12.2.2 Power Management ................................................................. 158
5.13.4.1 PCI Express* SCI .................................................................... 165
5.13.4.2 PCI Express* Hot-Plug ............................................................. 165
5.13.5.1 Slow C4 Exit (Mobile Only) ....................................................... 166
5.13.5.2 Transition Rules among S0/Cx and Throttling States .................... 167
5.13.5.3 Deferred C3/C4 (Mobile Only) ................................................... 167
5.13.5.4 POPUP (Auto C3/C4 to C2) (Mobile Only) .................................... 167
5.13.5.5 POPDOWN (Auto C2 to C3/C4) (Mobile Only)............................... 168
5.13.6.1 Conditions for Checking the PCI Clock ........................................ 168
5.13.6.2 Conditions for Maintaining the PCI Clock..................................... 168
5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 168
5.13.6.4 Conditions for Re-Starting the PCI Clock..................................... 169
5.13.6.5 LPC Devices and CLKRUN# ....................................................... 169
5.13.7.1 Sleep State Overview............................................................... 169
5.13.7.2 Initiating Sleep State ............................................................... 169
5.13.7.3 Exiting Sleep States................................................................. 170
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message ................... 172
5.13.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 172
5.13.8.1 THRM# Signal......................................................................... 173
5.13.8.2 Software Initiated Passive Cooling ............................................. 173
5.13.8.3 THRM# Override Software Bit ................................................... 173
5.13.8.4 Active Cooling......................................................................... 173
5.13.9.1 PWRBTN# (Power Button) ........................................................ 174
5.13.9.2 RI# (Ring Indicator) ................................................................ 175
5.13.9.3 PME# (PCI Power Management Event) ....................................... 175
5.13.9.4 SYS_RESET# Signal ................................................................ 175
5.13.9.5 THRMTRIP# Signal .................................................................. 176
5.13.9.6 BMBUSY# (Mobile Only) ........................................................... 176
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ICH8 and System Power States ..................................................... 160
Numeric Error)........................................................................ 157
(STPCLK# and CPUSLP#) ......................................................... 157
Intel
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ICH8 Family Datasheet