NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 528

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

528
21:8
Bit
23
22
7
6
5
4
3
2
1
0
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and
PxIS.IPMS are set, the ICH8 will generate an interrupt.
NOTE: Should be written as 0. Port Multiplier not supported by ICH8.
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
PxIS.PRCS is set, the ICH8 shall generate an interrupt.
Reserved - Should be written as 0
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the ICH8 will
generate an interrupt.
For systems that do not support an interlock switch, this bit shall be a read-only 0.
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
are set, the ICH8 will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
PxS.DPS are set, the ICH8 will generate an interrupt
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
unknown FIS is received, the ICH8 will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
PxS.SDBS are set, the ICH8 will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
are set, the ICH8 will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
are set, the ICH8 will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
GHC.IE and PxS.DHRS are set, the ICH8 will generate an interrupt.
Description
SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet