NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 674

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.9
674
GSTS—Global Status Register
(Intel
Memory Address:HDBAR + 10h
Default Value:
(Desktop
(Desktop
(Mobile
(Mobile
Only)
Only)
Only)
Only)
15:4
Bit
3
3
2
2
1
0
®
Reserved.
Dock Mated Interrupt Status (DMIS) — R/W/C. A 1 indicates that the dock
mating or unmating process has completed. For the docking process it indicates that
dock is electrically connected and that software may detect and enumerate the
docked codecs. For the undocking process it indicates that the dock is electrically
isolated and that software may report to the user that physical undocking may
commence. This bit gets set to a 1 by hardware when the DM bit transitions from a 0
to a 1 (docking) or from a 1 to a 0 (undocking). Note that this bit is set regardless of
the state of the DMIE bit.
Software clears this bit by writing a 1 to it. Writing a 0 to this bit has no affect.
Reserved
Dock Mated (DM)—RO. This bit effectively communicates to software that an Intel
HD Audio docked codec is physically and electrically attached.
Controller hardware sets this bit to 1 after the docking sequence triggered by writing
a 1 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_RST# deassertion).
This bit indicates to software that the docked codec(s) may be discovered via the
STATESTS register and then enumerated.
Controller hardware sets this bit to 0 after the undocking sequence triggered by
writing a 0 to the Dock Attach (GCTL.DA) bit is completed (DOCK_EN# deasserted).
This bit indicates to software that the docked codec(s) may be physically undocked.
This bit is Read Only. Writes to this bit have no effect.
Reserved
Flush Status — R/WC. This bit is set to 1 by hardware to indicate that the flush
cycle initiated when the Flush Control bit (HDBAR + 08h, bit 1) was set has
completed. Software must write a 1 to clear this bit before the next time the Flush
Control bit is set to clear the bit.
Reserved.
High Definition Audio Controller—D27:F0)
0000h
Intel
®
High Definition Audio Controller Registers (D27:F0)
Description
Attribute:
Size:
R/WC
16 bits
Intel
®
ICH8 Family Datasheet
®