NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 356

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.3
9.4
9.4.1
Table 107.
Note:
356
Counter Access Ports Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)
Interrupt Controller I/O MAP (LPC I/F—D31:F0)
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them.
different register possibilities for each address.
PIC Registers (LPC I/F—D31:F0)
Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section
7:0
4D0h
4D1h
Bit
Port
20h
21h
A0h
A1h
(Chapter
Counter Port — R/W. Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
34h, 38h, 3Ch
ADh, B1h,
2Dh, 31h,
A4h, A8h,
ACh, B0h,
B4h, B8h,
A5h, A9h,
B5h, B9h,
24h, 28h,
2Ch, 30h,
25h, 29h,
35h, 39h,
Aliases
BDh
3Dh
BCh
–
–
5.8).
Counter 0
Counter 1
Counter 2
All bits undefined
Master PIC ICW1 Init. Cmd Word 1
Master PIC OCW2 Op Ctrl Word 2
Master PIC OCW3 Op Ctrl Word 3
Master PIC ICW2 Init. Cmd Word 2
Master PIC ICW3 Init. Cmd Word 3
Master PIC ICW4 Init. Cmd Word 4
Master PIC OCW1 Op Ctrl Word 1
Slave PIC ICW1 Init. Cmd Word 1
Slave PIC OCW2 Op Ctrl Word 2
Slave PIC OCW3 Op Ctrl Word 3
Slave PIC ICW2 Init. Cmd Word 2
Slave PIC ICW3 Init. Cmd Word 3
Slave PIC ICW4 Init. Cmd Word 4
Slave PIC OCW1 Op Ctrl Word 1
Master PIC Edge/Level Triggered
Slave PIC Edge/Level Triggered
–
–
–
40h,
41h,
42h
Register Name
Description
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
001XXXXXb
X01XXX10b
001XXXXXb
X01XXX10b
Intel
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Default
Value
Table 107
01h
00h
01h
00h
00h
00h
®
ICH8 Family Datasheet
shows the
Type
R/W
R/W
R/W
R/W
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO