NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 407

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.14
Note:
Intel
®
ICH8 Family Datasheet
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the SMI status register.
31:26
24:19
16:15
10:8
Bit
25
18
17
14
13
12
11
7
Reserved
EL_SMI_EN — R/W.
0 = Disable
1 = Software sets this bit to enable Energy Lake logic to cause SMI#
Reserved
INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy USB2 logic to cause SMI#.
Reserved
PERIODIC_EN — R/W.
0 = Disable.
1 = Enables the ICH8 to generate an SMI# when the PERIODIC_STS bit (PMBASE +
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set,
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
Reserved
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables ICH8 to trap accesses to the microcontroller range (62h or 66h) and
Reserved
BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even
if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH8 on PCI,
but not forwarded to LPC.
to this bit position by BIOS software.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
PMBASE + 30h
00000000h
No
Core
Description
Attribute:
Size:
Usage:
R/W, R/W (special), WO
32 bit
ACPI or Legacy
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