NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 161

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 63.
Intel
®
ICH8 Family Datasheet
State Transition Rules for Intel
NOTES:
1.
2.
G0/S0/C0
G0/S0/C1
G0/S0/C2
G0/S0/C3
G0/S0/C4
G1/S3, or
Present
(Mobile
(Mobile
(Mobile
G1/S1,
G1/S4
G2/S5
State
Only)
Only)
Only)
G3
Some wake events can be preserved through power failure.
Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is
inactive in mobile configurations.
• Processor halt instruction
• Level 2 Read (Mobile Only)
• Level 3 Read (Mobile Only)
• SLP_EN bit set
• Power Button Override
• Mechanical Off/Power Failure
• Any Enabled Break Event
• STPCLK# goes active
• Power Button Override
• Power Failure
• Any Enabled Break Event
• Power Button Override
• Power Failure
• Previously in C3/C4 and bus masters
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Previously in C4 and bus masters idle
• Any Enabled Break Event
• Any Bus Master Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• Any Enabled Wake Event
• Power Failure
• Power Returns
Level 4 Read (Mobile Only)
idle
Transition Trigger
®
ICH8
• G0/S0/C1
• G0/S0/C2
• G0/S0/C2, G0/S0/C3 or G0/S0/C4 -
• G1/Sx or G2/S5 state
• G2/S5
• G3
• G0/S0/C0
• G0/S0/C2
• G2/S5
• G3
• G0/S0/C0
• G2/S5
• G3
• C3 or C4 - depending on PDME bit (D31:F0:
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
• G2/S5
• G3
• C4 - depending on PDME bit (D31:F0: Offset
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset A9h:
• G2/S5
• G3
• G0/S0/C0 (See Note 2)
• G2/S5
• G3
• G0/S0/C0 (See Note 2)
• G3
• Optional to go to S0/C0 (reboot) or G2/S5
depending on C4onC3_EN bit
(D31:F0:Offset A0h:bit 7) and
BM_STS_ZERO_EN bit (D31:F0:Offset
A9h:bit 2) (Mobile Only)
Offset A9h: bit 4)
bit 3) is set, else G0/S0/C0
A9h: bit 4
bit 3) is set, else G0/S0/C0
(stay off until power button pressed or other
wake event). (See Note 1 and 2)
Next State
161