NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 172

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13.7.4
5.13.7.5
Note:
Table 70.
172
PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using
the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH8 will set the PCI_EXP_STS bit.
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
The ICH8 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Transitions Due to Power Failure
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
State at Power Failure
(G3 state), the PWRBTN_STS bit is reset. When the ICH8 exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because V
standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
S0, S1, S3
S4
S5
AFTERG3_EN bit
1
0
1
0
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
Intel
®
Functional Description
ICH8 Family Datasheet
CC
-