NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 728

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.47
18.1.48
728
RPDCGEN—Root Port Dynamic Clock Gating Enable
(PCI Express-D28:F0/F1/F2/F3/F4/F5) (Mobile Only)
Address Offset: E1h
Default Value:
IPWS—Intel
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: E2h–E3h
Default Value:
14:0
Bits
7:4
Bit
15
3
2
1
0
Reserved. RO
Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN) — RW.
1 = Enables dynamic clock gating on the root port shared resource link clock domain.
0 = Disables dynamic clock gating of the shared resource link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5-6.
Shared Resource Dynamic Backbone Clock Gate Enable (SRDBCGEN) — RW.
1 = Enables dynamic clock gating on the root port shared resource backbone clock
domain.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5-6.
Root Port Dynamic Link Clock Gate Enable (RPDLCGEN) — RW.
1 = Enables dynamic clock gating on the root port link clock domain.
0 = Disables dynamic clock gating of the root port link clock domain.
Root Port Dynamic Backbone Clock Gate Enable (RPDBCGEN) — RW.
1 = Enables dynamic clock gating on the root port backbone clock domain.
0 = Disables dynamic clock gating of the root port backbone clock domain.
Intel PRO/Wireless 3945ABG Status (IPWSTAT) — RO. This bit is set if the link
has trained to L0 in Intel PRO/Wireless 3945ABG mode.
Reserved
00h
0007h
®
PRO/Wireless 3945ABG Status
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
R/W
8-bits
RO
16 bits
Intel
®
ICH8 Family Datasheet