NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 452

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.1.8
11.1.9
11.1.10
11.1.11
.
452
BCC—Base Class Code Register (IDE—D31:F1)
Address Offset:
Default Value:
CLS—Cache Line Size Register (IDE—D31:F1)
Address Offset:
Default Value:
PMLT—Primary Master Latency Timer Register
(IDE—D31:F1)
Address Offset:
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset:
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
15:3
2:1
7:0
7:0
7:0
Bit
Bit
Bit
Bit
0
Reserved
Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.
Base Class Code (BCC) — RO.
01 = Mass storage device
Cache Line Size (CLS) — RO.
00h = Hardwired. The IDE controller is implemented internally so this register has no
meaning.
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as
a PCI device, so it does not need a Master Latency Timer.
0Bh
01h
0Ch
00h
0Dh
00h
10h
00000001h
–
13h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1) (Mobile Only)
RO
8 bits
RO
R/W, RO
32 bits
8 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet