NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 311

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Gigabit LAN Configuration Registers
8.1.3
Intel
®
ICH8 Family Datasheet
PCICMD—PCI Command Register
(Gigabit LAN—D25:F0)
Address Offset: 04h–05h
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-
Plug and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port.
Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set.
Fast Back to Back Enable (FBE) — RO. Hardwired to ‘0’.
SERR# Enable (SEE) — R/W.
0 = Disable
1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is
Wait Cycle Control (WCC) — RO. Hardwired to ‘0’.
Parity Error Response (PER) — R/W.
0 = Disable.
1 = Indicates that the device is capable of reporting parity errors as a master on the
Palette Snoop Enable (PSE) — RO. Hardwired to ‘0’.
Postable Memory Write Enable (PMWE) — RO. Hardwired to ‘0’.
Special Cycle Enable (SCE) — RO. Hardwired to ‘0’.
Bus Master Enable (BME) — R/W.
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit
Memory Space Enable (MSE) — R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1 = Enable. Allows memory cycles within the range specified by the memory base and
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
power management and MSI is not enabled.
set.
backbone.
LAN* device.
registers are master aborted on the backbone.
limit registers can be forwarded to the Gigabit LAN device.
are master aborted on the backbone.
registers can be forwarded to the Gigabit LAN device.
0000h
Description
Attribute:
Size:
R/W, RO
16 bits
311