NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 69

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
Table 12.
2.9
Table 13.
Intel
®
ICH8 Family Datasheet
IDE Interface Signals (Mobile Only)
LPC Interface
LPC Interface Signals
WDMARDY#)
LFRAME# /
RDMARDY#)
LAD[3:0] /
LDRQ1# /
FWH[3:0]
DIOW# /
LDRQ0#
(DWSTB /
DIOR# /
IORDY /
(DRSTB /
DDACK#
(DSTOP)
GPIO23
Name
FWH4
Name
Type
Typ
I/O
O
O
O
O
I
e
I
IDE Device DMA Acknowledge: This signal directly drives the DAK#
signal on the IDE connector. DDACK# is asserted by the Intel
indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal
is used in conjunction with the PCI bus master IDE function and are not
associated with any AT-compatible DMA channel.
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the
IDE device that it may drive data onto the DD lines. Data is latched by the
ICH8 on the deassertion edge of DIOR#. The IDE device is selected either
by the ATA register file chip selects (DCS1# or DCS3#) and the DA lines,
or the IDE DMA acknowledge (DDAK#).
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe
for writes to disk. When writing to disk, ICH8 drives valid data on rising
and falling edges of DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for
reads from disk. When reading from disk, ICH8 deasserts RDMARDY# to
pause burst data transfers.
Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the DD lines. Data is latched
by the IDE device on the deassertion edge of DIOW#. The IDE device is
selected either by the ATA register file chip selects (DCS1# or DCS3#)
and the DA lines, or the IDE DMA acknowledge (DDAK#).
Disk Stop (Ultra DMA): ICH8 asserts this signal to terminate a burst.
I/O Channel Ready (PIO): This signal will keep the strobe active
(DIOR# on reads, DIOW# on writes) longer than the minimum width. It
adds wait-states to PIO transfers.
Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk,
ICH8 latches data on rising and falling edges of this signal from the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is
de-asserted by the disk to pause burst data transfers.
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal
pull-ups are provided.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
request DMA or bus master access. These signals are typically connected
to external Super I/O device. An internal pull-up resistor is provided on
these signals.
LDRQ1# may optionally be used as GPIO.
Description
Description
®
ICH8 to
69