NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 632

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2.1
632
HST_STS—Host Status Register (SMBUS—D31:F3)
Register Offset: SMBASE + 00h
Default Value:
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a 0 to any bit position has no effect.
Bit
7
6
5
4
3
2
Byte Done Status (DS) — R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
NOTE: When the last byte of a block message is received, the host controller will set
INUSE_STS — R/WC (special). This bit is used as semaphore among various
independent software threads that may need to use the ICH8’s SMBus logic, and has no
other effect on hardware.
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will
SMBALERT_STS — R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only
If the signal is programmed as a GPIO, then this bit will never be set.
FAILED — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in
BUS_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt of SMI# was a transaction collision.
DEV_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it. The ICH8 will then deassert the
1 = The source of the interrupt or SMI# was due to one of the following:
• Invalid Command Field,
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.
transmission of a byte (for Block Write commands) when the 32-byte buffer is not
being used. Note that this bit will be set, even on the last byte of the transfer. This
bit is not set when transmission is due to the LAN interface heartbeat.
reset the next read value to 0. Writing a 0 to this bit has no effect. Software can
poll this bit until it reads a 0, and will then own the usage of the host controller.
writing a 1 to it.
cleared by software writing a 1 to the bit position or by RSMRST# going low.
response to the KILL bit being set to terminate the host transaction.
interrupt or SMI#.
this bit. However, it will not immediately set the INTR bit (bit 1 in this register).
When the interrupt handler clears the DS bit, the message is considered
complete, and the host controller will then set the INTR bit (and generate
another interrupt). Thus, for a block message of n bytes, the ICH8 will generate
n+1 interrupts. The interrupt handler needs to be implemented to handle these
cases. When not using the 32 Byte Buffer, hardware will drive the SMBCLK
signal low when the DS bit is set until SW clears the bit. This includes the last
byte of a transfer. Software must clear the DS bit before it can clear the BUSY
bit.
00h
Attribute:
Size:
Description
8-bits
R/WC, R/WC (special), RO
SMBus Controller Registers (D31:F3)
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ICH8 Family Datasheet