NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 553

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F5)
13.1.28
13.1.29
Intel
®
ICH8 Family Datasheet
PMCS—PCI Power Management Control and Status
Register (SATA–D31:F5)
Address Offset: 74h
Default Value:
MAP—Address Map Register (SATA–D31:F5)
Address Offset: 90h
Default Value:
14:9
Bits
Bits
7:4
1:0
7:2
1:0
15
8
3
2
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller
Reserved
PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form
D3
Reserved
No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices
transitioning from D3
0 = Device transitioning from D3
1 = Device transitioning from D3
Configuration content is preserved. Upon transition from the D3
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the
SATA controller and to set a new power state.
00 = D0 state
11 = D3
When in the D3
and memory spaces are not. Additionally, interrupts are blocked.
Reserved.
Map Value — RO. Map Value (MV): This field is hardwired to read-only ‘00’ indicating
the controller shall support two logical master devices with Port 0 and Port 1 being
mapped to Primary Channel and Secondary Channel Respectively
HOT
on a wake event.
HOT
0008h
00h
state
–
HOT
75h
state, the controller’s configuration space is available, but the I/O
HOT
state to D0 state will perform an internal reset.
HOT
HOT
state to D0 state do not perform an internal reset.
state to D0 state perform an internal reset.
Description
Description
Attribute:
Size:
Attribute:
Size:
HOT
state to D0 state by a system
RO, R/W, R/WC
16 bits
RO
8 bits
HOT
state to D0 state
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