NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 118

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.2.1
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Gigabit Ethernet Controller (B0:D25:F0)
The ICH8 integrates a Gigabit Ethernet Controller. The integrated GbE controller is
compatible with Intel 10/100 PHY (Intel® 82562V Platform LAN Connect device) and
GbE PHY (Intel
controller provides two interfaces: LCI for 10/100 operation and GLCI for GbE
operation. The GLCI is shared with the ICH8’s PCI Express port 6 and can be enabled
via a soft strap that is stored in system SPI flash.
The ICH8 integrated GbE controller supports multi speed operation, 10/100/1000 Mb/s.
The integrated GbE can operate in full-duplex at all supported speed or half-duplex at
10/100 Mb/s, and adheres with the IEEE 802.3x Flow Control Specification.
The controller provides a system interface via a PCI function. A full memory-mapped or
I/O-mapped interface is provided to the software, along with DMA mechanisms for high
performance data transfer.
The following summarizes the ICH8 integrated GbE controller features:
GbE PCI Bus Interface
The GbE controller has a PCI interface to the host processor and host memory. The
following sections detail the transaction on the bus.
Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer
connects to the device core using an implementation specific protocol. Through this
core-to-transaction-layer protocol, the application-specific parts of the device interact
with the subsystem and transmit and receive requests to or from the remote agent,
respectively.
Data Alignment
4K Boundary
PCI requests must never specify an Address/Length combination that causes a Memory
Space access to cross a 4K boundary. It is the HW responsibility to break requests into
4K-aligned requests (if needed). This does not pose any requirement on SW. However,
if SW allocates a buffer across a 4K boundary, HW will issue multiple requests for the
buffer. SW should consider aligning buffers to 4KB boundary in cases where it improves
performance.
The alignment to the 4K boundaries is done in the core. The Transaction layer will not
do any alignment according to these boundaries.
• Configurable LED operation for customization of LED display.
• IPv4 and IPv6 Checksum Offload support (receive, transmit, and large send)
• 64-bit address master support for system using more than 4 GB of physical
• Configurable receive and transmit data FIFO, programmable in 1 KB increments.
• Intelligent interrupt generation to enhance driver performance
• Compliance with Advanced Configuration and Power Interface and PCI Power
• ACPI register set and power down functionality supporting D0 & D3 states
• Full wake-up support (ACPI)
• Magic Packet wake-up enable with unique MAC address
• Fragmented UDP checksum off load for package reassembly
memory.
Management standards
®
82566 Gigabit Platform LAN Connect device). The integrated GbE
Intel
®
Functional Description
ICH8 Family Datasheet