NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 428

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10.9
9.10.10
428
GPI_INV—GPIO Signal Invert Register
Offset Address: GPIOBASE +2Ch
Default Value:
Lockable:
GPIO_USE_SEL2—GPIO Use Select 2 Register[63:32]
Offset Address: GPIOBASE +30h
Default Value:
Lockable:
31:0
31:0
Bit
Bit
GP_INV[n] — R/W. Input Inversion: This bit only has effect if the corresponding
GPIO is used as an input and used by the GPE logic, where the polarity matters. When
set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit
has no effect on the value that is reported in the GP_LVL register.
These bits are used to allow both active-low and active-high inputs to cause SMI# or
SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the ICH8. In the S3, S4 or S5 states the input signal must
be active for at least 2 RTC clocks to ensure detection. The setting of these bits has no
effect if the corresponding GPIO is programmed as an output. These bits correspond to
GPI that are in the resume well, and will be reset to their default values by RSMRST# or
by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the ICH8 detects the state of the input
1 = The corresponding GPI_STS bit is set when the ICH8 detects the state of the input
GPIO_USE_SEL2[31:0]— R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1.
2.
3.
4.
5.
pin to be high.
pin to be low.
The following bit is always 1 because it is always unmultiplexed: 0.
If GPIO[n] does not exist, then the (n-32) bit in this register will always read as
0 and writes will have no effect. The following bits are always 0: [15:12],
[31:24].
When RSMRST# is asserted, all multiplexed signals in the resume and core
wells are configured as their default function. when just PLTRST# is asserted,
the GPIOs in the core well are configured as their default function.
When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
All GPIOs are reset to the default state by CF9h reset (except GPIO24)
00000000h
No
000100FFh (Desktop)
000100FEh (Mobile)
No
Attribute:
Size:
Power Well:
Description
Description
Attribute:
Size:
Power Well: Core for
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
CPU I/O for 17, Core for 16, 7:0
32-bit
R/W
0:7, 16:23, Resume for 8:15,
24:31
Intel
®
ICH8 Family Datasheet