NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 688

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.36
688
SDCTL—Stream Descriptor Control Register
(Intel
Memory Address:Input Stream[0]: HDBAR + 80hAttribute:
Default Value:
23:20
17:16
15:5
Bit
19
18
4
3
2
Stream Number — R/W. This value reflects the Tag associated with the data being
transferred on the link. When data controlled by this descriptor is sent out over the link,
it will have its stream number encoded on the SYNC signal. When an input stream is
detected on any of the SDI signals that match this value, the data samples are loaded
into FIFO associated with this descriptor.
NOTE: While a single SDI input may contain data from more than one stream number,
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional
streams; therefore, this bit is hardwired to 0.
Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is
enabled through the PCI Express* registers.
Stripe Control — RO. This bit is only meaningful for input streams; therefore, this bit is
hardwired to 0.
Reserved
Descriptor Error Interrupt Enable — R/W.
0 = Disable
1 = Enable. An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable — R/W. This bit controls whether the occurrence of a
FIFO error (overrun for input or underrun for output) will cause an interrupt. If this bit
is not set, bit 3in the Status register will be set, but the interrupt will not occur. Either
way, the samples will be dropped.
Interrupt on Completion Enable — R/W. This bit controls whether or not an interrupt
occurs when a buffer completes with the IOC bit set in its descriptor. If this bit is not
set, bit 2 in the Status register will be set, but the interrupt will not occur.
®
High Definition Audio Controller—D27:F0)
two different SDI inputs may not be configured with the same stream number.
Input Stream[1]: HDBAR + A0h
Input Stream[2]: HDBAR + C0h
Input Stream[3]: HDBAR + E0h
Output Stream[0]: HDBAR + 100h
Output Stream[1]: HDBAR + 120h
Output Stream[2]: HDBAR + 140h
Output Stream[3]: HDBAR + 160h
040000h
Intel
®
Description
High Definition Audio Controller Registers (D27:F0)
Size:
R/W, RO
24 bits
Intel
®
ICH8 Family Datasheet