NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 382

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC
5:4
Bit
3
2
1
0
clock period may not be detected by the ICH8.
SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum
assertion width of the SLP_S4# signal to assure that the DRAMs have been safely
power-cycled.
Valid values are:
11 = 1 to 2 seconds
10 = 2 to 3 seconds
01 = 3 to 4 seconds
00 = 4 to 5 seconds
This value is used in two ways:
1.
2.
RTCRST# forces this field to the conservative default state (00b)
SLP_S4# Assertion Stretch Enable — R/W.
0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this
This bit is cleared by RTCRST#
RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates
a weak or missing battery. The bit is not cleared by any type of reset. The bit will
remain set until the software clears it by writing a 0 back to this bit position.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by
any type of reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was
1 = Indicates that the trickle current (from the main battery or trickle supply) was
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on
AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied
after a power failure (G3 state). This bit is in the RTC well and is not cleared by any
type of reset except writes to CF9h or RTCRST#.
0 = System will return to S0 state (boot) after power is re-applied.
1 = System will return to the S5 state (except if it was in S4, in which case it will return
NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.
register.
cleared. Software clears this bit by writing a 1 to it.
removed or failed.
to S4). In the S5 state, the only enabled wake event is the Power Button or any
enabled wake event that was preserved through the power failure.
If the SLP_S4# assertion width is ever shorter than this time, a status bit is set
for BIOS to read when S0 is entered.
If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal
from deasserting within this minimum time period after asserting.
RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet