NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 306

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.72
306
CG—Clock Gating (Mobile Only)
Offset Address: 341C–341Fh
Default Value:
29:28
18:17
Bit
31
30
27
26
25
24
23
22
21
20
19
16
Legacy (LPC) Dynamic Clock Gate Enable — R/W.
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
PATA Dynamic Clock Gate Enable — R/W.
0 = PATA Dynamic Clock Gating is Disabled
1 = PATA Dynamic Clock Gating is Enabled
USB UHCI Dynamic Clock Gate Enable — R/W.
0 = USB UHCI Dynamic Clock Gating is Disabled
1 = USB UHCI Dynamic Clock Gating is Enabled
0 = Reserved
1 = Reserved
Reserved
SATA Port 2 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 2 Dynamic Clock Gating is Disabled
1 = SATA Port 2 Dynamic Clock Gating is Enabled
SATA Port 1 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 1 Dynamic Clock Gating is Disabled
1 = SATA Port 1 Dynamic Clock Gating is Enabled
SATA Port 0 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 0 Dynamic Clock Gating is Disabled
1 = SATA Port 0 Dynamic Clock Gating is Enabled
LAN Static Clock Gating Enable (LANSCGE) — R/W.
0 = LAN Static clock gating is disabled
1 = LAN Static clock gating is enabled when the LAN Disable bit is set in the Function
High Definition Audio Dynamic Clock Gate Enable — R/W.
0 = High Definition Audio Dynamic Clock Gating is Disabled
1 = High Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable — R/W.
0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
Reserved
PCI Dynamic Gate Enable — R/W.
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
Disable SUS Well register.
00000000h
Description
Attribute:
Size:
Chipset Configuration Registers
R/W, RO
32-bit
Intel
®
ICH8 Family Datasheet