NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 435

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI-to-PCI Bridge Registers (D30:F0)
10.1.5
10.1.6
Intel
®
ICH8 Family Datasheet
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Default Value:
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h-0Bh
Default Value:
23:16
10:9
15:8
7:0
7:5
2:0
Bit
7:0
Bit
Bit
11
8
4
3
Revision ID — RO. Refer to the Intel
Specification Update for the value of the Revision ID Register
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
Reserved.
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
Reserved.
Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI
bridge.
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
Reserved
Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is
subtractive decode
backbone.
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04,
bit 6).
See bit description
060401h
Description
Description
Description
®
I/O Controller Hub 8 (ICH8) Family
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
24 bits
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