NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 89

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
Table 30.
Intel
HDA_DOCK_EN#
LAN100_SLP
®
INTVRMEN
SATALED#
SPI_CS1#
GPIO33 /
GNT0#,
ICH8 Family Datasheet
Signal
SPKR
TP3
Functional Strap Definitions (Sheet 2 of 2)
NOTE:
1.
2.
Flash Descriptor Security
Integrated VccSus1_05,
Integrated VccLAN1_05
Boot BIOS Destination
VccCL1_5 VRM Enable
Reversal (Lanes 1–4)
and VccCL1_05 VRM
XOR Chain Entrance
See
When strapped, the SPI_CS1# pin is required to be held at the strapped value for the
minimum of 200 ns with respect to the rising edge of either the CLPWROK pin or the
LAN_RST# pin, whichever rises first. Note that the hold time is also required to meet the
minimum of 101 ms after the RSMRST# pin is deasserted in the case both ICH8 ME well
and AUX well are connected to the Resume Well power.
PCI Express Lane
VccSus1_5, and
Override Strap
No Reboot
Section
Selection
Usage
Enable
3.1for full details on pull-up/pull-down resistors.
Rising Edge of
Rising Edge of
Rising Edge of
Rising Edge of
Rising Edge of
Sampled
(Note 1)
PWROK
PWROK
PWROK
PWROK
PWROK
Always
Always
When
This field determines the destination of accesses
to the BIOS memory range. Signals have weak
internal pull-ups. Also controllable via Boot BIOS
Destination bit (Chipset Configuration
Registers:Offset 3410h:bit 11:10).
(GNT0# is MSB)
01 = SPI
10 = PCI
11 = LPC
NOTE: Booting to PCI is intended for debug/
Enables integrated VccSus1_05, VccSus1_5 and
VccCL1_5 VRMs. Pin must be pulled-up to
VccRTC.
Enables integrated VccLAN1_05 and VccCL1_05
VRMs. Pin must be pulled-up to VccRTC.
Signal has weak internal pull-up.
Sets bit 27 of MPC.LR (Device 28: Function 0:
Offset D8)
The signal has a weak internal pull-down. If the
signal is sampled high, this indicates that the
system is strapped to the “No Reboot” mode
(ICH8 will disable the TCO Timer system reboot
feature). The status of this strap is readable via
the NO REBOOT bit (Chipset Configuration
Registers:Offset 3410h:bit 5).
See
This signal has a weak internal pull-up.
NOTE: This signal should not be pulled low
This signal has a weak internal pull-up. If
sampled low, the Flash Descriptor Security will
be overridden. If high, the security measures
defined in the Flash Descriptor will be in effect.
NOTE: This should only be used in
Chapter 29
testing only. Boot BIOS Destination
Select to LPC/PCI by functional strap or
via Boot BIOS Destination Bit will not
affect SPI accesses initiated by ME or
Integrated GbE LAN.
unless using XOR Chain testing.
manufacturing environments.
for functionality information.
Comment
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