NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 218

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 16.
5.19.8.2
218
Note that the port-routing logic is the only block of logic within the ICH8 that observes
the physical (real) connect/disconnect information. The port status logic inside each of
the host controllers observes the electrical connect/disconnect information that is
generated by the port-routing logic.
Only the differential signal pairs are multiplexed/demultiplexed between the UHCI and
EHCI host controllers. The other USB functional signals are handled as follows:
The Port-Routing logic is implemented in the Suspend power well so that re-
enumeration and re-mapping of the USB ports is not required following entering and
exiting a system sleep state in which the core power is turned off.
The ICH8 also allows the USB Debug Port traffic to be routed in and out of Port #0.
When in this mode, the Enhanced Host controller is the owner of Port 0.
Device Connects
The Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision
1.0 describes the details of handling Device Connects in Section 4.2. There are four
general scenarios that are summarized below.
Intel
1. Configure Flag = 0 and a full-speed/low-speed-only Device is connected
2. Configure Flag = 0 and a high-speed-capable Device is connected
3. Configure Flag = 1 and a full-speed/low-speed-only Device is connected
• The Overcurrent inputs (OC[9:0]#) are directly routed to both controllers. An
Port
overcurrent event is recorded in both controllers’ status registers.
— In this case, the UHC is the owner of the port both before and after the connect
— In this case, the UHC is the owner of the port both before and after the connect
— In this case, the EHC is the owner of the port before the connect occurs. The
0
®
UHCI 1
occurs. The EHC (except for the port-routing logic) never sees the connect
occur. The UHCI driver handles the connection and initialization process.
occurs. The EHC (except for the port-routing logic) never sees the connect
occur. The UHCI driver handles the connection and initialization process. Since
the UHC does not perform the high-speed chirp handshake, the device operates
in compatible mode.
EHCI driver handles the connection and performs the port reset. After the reset
process completes, the EHC hardware has cleared (not set) the Port Enable bit
in the EHC’s PORTSC register. The EHCI driver then writes a 1 to the Port Owner
ICH8-USB Port Connections
UHC
I
Device 29 EHCI
Port
Port
1
1
Port
Port
2
2
UHCI 2
UHC
I
Port
Port
3
3
Port
Port
4
4
UHCI 3
UHC
I
Port
Port
5
5
Port
Port
6
6
UHCI 4
UHC
Device 26 EHCI
I
Port
Port
7
7
Intel
®
Functional Description
ICH8 Family Datasheet
Port
Port
8
8
UHCI 5
UHC
I
Port
Port
9
9