NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 443

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI-to-PCI Bridge Registers (D30:F0)
10.1.21
Intel
®
ICH8 Family Datasheet
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44h
Default Value:
29: 8
7: 6
Bit
31
30
5
4
3
Discard Delayed Transactions (DDT) — R/W.
0 = Logged delayed transactions are kept.
1 = The ICH8 PCI bridge will discard any delayed transactions it has logged. This
NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will
Block Delayed Transactions (BDT) — R/W.
0 = Delayed transactions accepted
1 = The ICH8 PCI bridge will not accept incoming transactions which will result in
Reserved
Maximum Delayed Transactions (MDT) — R/W. Controls the maximum number of
delayed transactions that the ICH8 PCI bridge will run. Encodings are:
00 =) 2 Active, 5 pending
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
Reserved
Auto Flush After Disconnect Enable (AFADE) — R/W.
0 = The PCI bridge will retain any fetched data until required to discard by producer/
1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-
Never Prefetch (NP) — R/W.
0 = Prefetch enabled
1 = The ICH8 will only fetch a single DW and will not enable prefetching, regardless of
includes transactions in the pending queue, and any transactions in the active
queue, whether in the hard or soft DT state. The prefetchers will be disabled and
return to an idle state.
delayed transactions. It will blindly retry these cycles by asserting STOP#. All
postable cycles (memory writes) will still be accepted.
consumer rules.
asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI
transfer.
the command being an Memory read (MR), Memory read line (MRL), or Memory
read multiple (MRM).
continue until either the PCI master disconnects (by de-asserting FRAME#) or
the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI
bridge when the delayed transaction queues are empty and have returned to an
idle state. Software sets this bit and polls for its completion
00000000h
–
47h
Description
Attribute:
Size:
R/W, RO
32 bits
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