NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 405

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.13
Intel
®
ICH8 Family Datasheet
GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits
are cleared by RTCRST#.
(Desktop
(Mobile
31:16
Only)
Only)
Bit
15
14
13
12
11
10
10
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16
Reserved
USB4_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB4_STS bit to generate a wake event. The
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The
PME_EN — R/W.
0 = Disable.
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
QRT_SCI_EN — R/W. In Desktop Mode this bit enables the QRT_SCI_STS signal to
cause an SCI (depending on the SCI_EN bit) when it is asserted
BATLOW_EN — R/W.
0 = Disable.
1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the
USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event.
Break events are handled via the USB interrupt.
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event.
Break events are handled via the USB interrupt.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal
from inhibiting the wake event.
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
00000000h
No
Bits 0–7, 9, 12, 14–31 Resume,
Bits 8, 10–11, 13 RTC
corresponds to GPIO0.
Description
Attribute:
Size:
Usage:
R/W
32-bit
ACPI
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