NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 475

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.1.19
12.1.20
12.1.21
Note:
Intel
®
ICH8 Family Datasheet
INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh
Default Value:
IDE_TIM — IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA
transfers. It also controls operation of the buffer for PIO transfers.
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation unless otherwise noted.
13:12
7:0
Bit
7:0
Bit
Bit
15
14
Interrupt Line — R/W. This field is used to communicate to software the interrupt line
that the interrupt pin is connected to.
Interrupt Pin — RO. This reflects the value of D31IP.SIP (Chipset Configuration
Registers: Offset 3100h:bits 11:8).
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number
of PCI clocks between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
primary, 170–177h for secondary) and Control Block (3F6h for primary and 376h
for secondary).
See
00h
See Register Description
Secondary: 42h
0000h
Section 5.16
®
ICH8 to decode the associated Command Blocks (1F0–1F7h for
–
for more on ATA modes of operation.
41h
–
43h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
RO
8 bits
R/W
16 bits
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