NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 576

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2.1
576
USBCMD—USB Command Register
I/O Offset:
Default Value:
The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
provides additional information on the operation of the Run/Stop and Debug bits.
15:7
Bit
8
7
6
5
4
3
Reserved
Loop Back Test Mode — R/W.
0 = Disable loop back test mode.
1 = ICH8 is in loop back test mode. When both ports are connected together, a write to
Max Packet (MAXP) — R/W. This bit selects the maximum packet size that can be
used for full speed bandwidth reclamation at the end of a frame. This value is used by
the host controller to determine whether it should initiate another transaction based on
the time remaining in the SOF counter. Use of reclamation packets larger than the
programmed size will cause a Babble error if executed during the critical window at
frame end. The Babble error results in the offending endpoint being stalled. Software is
responsible for ensuring that any packet which could be executed under bandwidth
reclamation be within this size limit.
0 = 32 bytes
1 = 64 bytes
Configure Flag (CF) — R/W. This bit has no effect on the hardware. It is provided only
as a semaphore service for software.
0 = Indicates that software has not completed host controller configuration.
1 = HCD software sets this bit as the last action in its process of configuring the host
Software Debug (SWDBG) — R/W. The SWDBG bit must only be manipulated when
the controller is in the stopped state. This can be determined by checking the HCHalted
bit in the USBSTS register.
0 = Normal Mode.
1 = Debug mode. In SW Debug mode, the host controller clears the Run/Stop bit after
Force Global Resume (FGR) — R/W.
0 = Software resets this bit to 0 after 20 ms has elapsed to stop sending the Global
1 = Host controller sends the Global Resume signal on the USB, and sets this bit to 1
Enter Global Suspend Mode (EGSM) — R/W.
0 = Software resets this bit to 0 to come out of Global Suspend mode. Software writes
1 = Host controller enters the Global Suspend mode. No USB transactions occur during
one port will be seen on the other port and the data will be stored in I/O offset 18h.
controller.
the completion of each USB transaction. The next transaction is executed when
software sets the Run/Stop bit back to 1.
Resume signal. At that time all USB devices should be ready for bus activity. The 1
to 0 transition causes the port to send a low speed EOP signal. This bit will remain
a 1 until the EOP has completed.
when a resume event (connect, disconnect, or K-state) is detected while in global
suspend mode.
this bit to 0 at the same time that Force Global Resume (bit 4) is written to 0 or
after writing bit 4 to 0.
this time. The Host controller is able to receive resume signals from USB and
interrupt the system. Software must ensure that the Run/Stop bit (bit 0) is cleared
prior to setting this bit.
BASE + (00h
0000h
–
01h)
Description
Attribute:
Size:
R/W
16 bits
UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet
Table 132