NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 607

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.2.2
Table 135.
Note:
Intel
®
ICH8 Family Datasheet
Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities registers. The operational register base must be
dword-aligned and is calculated by adding the value in the first capabilities register
(CAPLENGTH) to the base address of the enhanced host controller register address
space (MEM_BASE). Since CAPLENGTH is always 20h,
this offset. All registers are 32 bits in length.
Enhanced Host Controller Operational Register Address Map
Software must read and write these registers using only dword accesses.These
registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
MEM_BASE
• Core well hardware reset
• HCRESET
• D3-to-D0 reset
B4h–3FFh
D29 Only
D29 Only
+ Offset
28h–2Bh
38h–3Bh
68h–6Bh
78h–7Bh
A0h–B3h
20h–23h
24h–27h
2Ch–2Fh
30h–33h
34h–37h
3Ch–5Fh
60h–63h
64h–67h
6Ch–6Fh
70h–73h
74h–77h
7Ch–9Fh
ASYNCLISTAD
CTRLDSSEGM
USB2.0_INTR
PERODICLIST
USB2.0_CMD
CONFIGFLAG
USB2.0_STS
Mnemonic
PORT0SC
PORT1SC
PORT2SC
PORT3SC
PORT4SC
PORT5SC
FRINDEX
BASE
ENT
DR
—
—
—
—
USB 2.0 Command
USB 2.0 Status
USB 2.0 Interrupt Enable
USB 2.0 Frame Index
Control Data Structure
Segment
Period Frame List Base
Address
Current Asynchronous
List Address
Reserved
Configure Flag
Port 0 Status and Control
Port 1 Status and Control
Port 2 Status and Control
Port 3 Status and Control
Port 4 Status and Control
Port 5 Status and Control
Reserved
Debug Port Registers
Reserved
Register Name
00080000h
00001000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
Undefined
Undefined
Undefined
Table 135
Default
0h
already accounts for
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Special
Notes
See register
description
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
Type
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W,
R/W
R/W
R/W
R/W
RO
RO
RO
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