NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 182

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
5.13.11.6
5.13.11.7
5.13.12
Table 76.
182
When VRMPWRGD goes inactive, a host power cycle and global reset will occur.
BATLOW# (Battery Low) (Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI# if the system is already in an S0 state.
Controlling Leakage and Power Consumption
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some low-
power states.
General principles:
Based on the above principles, the following measures are taken:
Clock Generators
The clock generator is expected to provide the frequencies shown in
Intel
• All signals going to powered down planes (either internally or externally) must be
• Signals with pull-up resistors should not be low during low-power states. This is to
• Buses should be halted (and held) in a known state to avoid a floating input
• During S3 (STR), all signals attached to powered down planes are tri-stated or
SATA_CLK
DMI_CLK
LAN_CLK
Domain
PCICLK
either tri-stated or driven low.
avoid the power consumed in the pull-up resistor.
(perhaps to some other device). Floating inputs can cause extra power
consumption.
driven low.
CLK48
CLK14
Clock
®
ICH8 Clock Inputs
48.000 MHz
14.318 MHz
Frequency
Differential
Differential
100 MHz
100 MHz
33 MHz
50 MHz
0.8 to
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Generator
Generator
Generator
Generator
Generator
Connect
Source
LAN
Used by SATA controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by DMI and PCI Express*. Stopped in S3 ~ S5
based on SLP_S3# assertion.
Desktop: Free-running PCI Clock to ICH8. Stopped in
S3 ~ S5 based on SLP_S3# assertion.
Mobile: Free-running (not affected by STP_PCI# PCI
Clock to ICH8. This is not the system PCI clock. This
clock must keep running in S0 while the system PCI
clock may stop based on CLKRUN# protocol. Stopped
in S3 ~ S5 based on SLP_S3# assertion.
Used by USB controllers and Intel
Audio controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by ACPI timers. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
LAN Connect Interface. Control policy is determined
by the clock source.
Usage
Intel
®
Functional Description
®
Table
ICH8 Family Datasheet
High Definition
76.