NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 745

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Precision Event Timer Registers
Intel
®
ICH8 Family Datasheet
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any
Bit
8
7
6
5
4
3
2
1
0
unimplemented registers will return an undetermined value.
Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set
this bit to force a 64-bit timer to behave as a 32-bit timer.
Timer 0:
Timers 1, 2:
NOTE: When this bit is set to ‘1’, the hardware counter will do a 32-bit operation on
Reserved. This bit returns 0 when read.
Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only
for Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software
is then allowed to directly set the timer’s accumulator. Software does not have to
write this bit back to 1 (it automatically clears).
Software should not write a 1 to this bit position if the timer is set to non-periodic
mode.
NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it
Timer n Size (TIMERn_SIZE_CAP) — RO. This read only field indicates the size of
the timer.
Timer 0:
Timers 1, 2:
Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the
hardware supports a periodic mode for this timer’s interrupt.
Timer 0:
Timers 1, 2:
Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
Timer 0:
Timers 1, 2:
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set
to enable timer n to cause an interrupt when it times out.
1 = Enable.
0 = Disable (Default). The timer can still count and generate appropriate status bits,
Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.
0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is
1 = The timer interrupt is level triggered. This means that a level-triggered interrupt
Reserved. These bits will return 0 when read.
but will not cause an interrupt.
generated. If another interrupt occurs, another edge will be generated.
is generated. The interrupt will be held active until it is cleared by writing to the
bit in the General Interrupt Status Register. If another interrupt occurs before the
interrupt is cleared, the interrupt will remain active.
comparator match and rollovers, thus the upper 32-bit of the Timer 0
Comparator Value register is ignored. The upper 32-bit of the main counter is
not involved in any rollover from lower 32-bit of the main counter and
becomes all zeros.
is set to periodic mode. Writes will have no effect for Timers 1 and 2.
Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit
Hardwired to 0. Writes have no effect (since these two timers are 32-
bits).
Value is 1 (64-bits).
Value is 0 (32-bits).
Hardwired to 1 (supports the periodic interrupt).
Hardwired to 0 (does not support periodic interrupt).
Bit is read/write. 0 = Disable timer to generate periodic interrupt;
1 = Enable timer to generate a periodic interrupt.
Hardwired to 0. Writes have no affect.
Description
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