MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 132

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
Reset Controller Module
5.6 Memory Map and Registers
Technical Data
132
The reset controller programming model consists of the following
registers:
1. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only
2. Within the specified module memory map, accessing reserved addresses does not
Freescale Semiconductor, Inc.
addresses have no effect and result in a a cycle termination transfer error.
generate a bus error exception. Reads of reserved addresses return 0s and writes have
no effect.
0x000c4_0000
0x000c4_0001
0x000c4_0002
0x000c4_0003
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Reset control register (RCR) — Selects interrupt controller
functions
Reset status register (RSR) — Reflects the state of the last reset
source
Reset test register (RTR) — Used only for factory test
Address
Table 5-2. Reset Controller Module Memory Map
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Reset Controller Module
Reset control register (RCR)
Reset status register (RSR)
Reset test register (RTR)
Reserved
Bits 7–0
(2)
MMC2107 – Rev. 2.0
Access
MOTOROLA
S/U
S/U
S/U
(1)