MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 156

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Interrupt Controller Module
7.7.1 Memory Map
Technical Data
156
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
0x00c5_0000
0x00c5_0004
0x00c5_0008
0x00c5_0010
0x00c5_0014
0x00c5_0018
0x00c5_0020
0x00c5_0040
0x00c5_0044
0x00c5_0048
0x00c5_0050
0x00c5_0054
0x00c5_0058
0x00c5_0060
0x00c5_0064
0x00c5_0068
0x00c5_000c
0x00c5_001c
0x00c5_003c
0x00c5_004c
0x00c5_005c
0x00c5_007c
only addresses have no effect and result in a cycle termination transfer error.
Address
through
through
Bits 31–24
Interrupt control register (ICR)
Table 7-1. Interrupt Controller Module Memory Map
PLSR12
PLSR16
PLSR20
PLSR24
PLSR28
PLSR32
PLSR36
PLSR0
PLSR4
PLSR8
Freescale Semiconductor, Inc.
Priority level select registers (PLSR0–PLSR39)
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Normal interrupt pending register (NIPR)
Normal interrupt enable register (NIER)
Fast interrupt pending register (FIPR)
Fast interrupt enable register (FIER)
Interrupt force register high (IFRH)
IInterrupt force register low (IFRL)
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Interrupt Controller Module
Bits 23–16
Interrupt pending register (IPR)
PLSR13
PLSR17
PLSR21
PLSR25
PLSR29
PLSR33
PLSR37
PLSR1
PLSR5
PLSR9
Unimplemented
Unimplemented
Bits 15–8
Interrupt status register (ISR)
PLSR10
PLSR14
PLSR18
PLSR22
PLSR26
PLSR30
PLSR34
PLSR38
(2)
PLSR2
PLSR6
(2)
Bits 7–0
PLSR11
PLSR15
PLSR19
PLSR23
PLSR27
PLSR31
PLSR35
PLSR39
PLSR3
PLSR7
MMC2107 – Rev. 2.0
MOTOROLA
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
S
S
S
S
S
S
S
S
S
(1)