MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 304

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
Timer Modules (TIM1 and TIM2)
15.7.5 Timer Counter Registers
Technical Data
304
Address: TIM1 — 0x00ce_0004
Address: TIM1 — 0x00ce_0005
Reset:
Reset:
Read: Anytime
Write: Only in test (special) mode; has no effect in normal modes
To ensure coherent reading of the timer counter, such that a timer
rollover does not occur between two back-to-back 8-bit reads, it is
recommended that only half-word (16-bit) accesses be used.
A write to TIMCNT may have an extra cycle on the first count because
the write is not synchronized with the prescaler clock. The write occurs
at least one cycle before the synchronization of the prescaler clock.
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
TIM2 — 0x00cf_0004
TIM2 — 0x00cf_0005
Figure 15-6. Timer Counter Register High (TIMCNTH)
Figure 15-7. Timer Counter Register Low (TIMCNTL)
Bit 15
Bit 7
Bit 7
Bit 7
0
0
Timer Modules (TIM1 and TIM2)
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= Writes have no effect and the access terminates without a transfer error exception.
= Writes have no effect and the access terminates without a transfer error exception.
14
6
0
6
6
0
13
5
0
5
5
0
12
4
0
4
4
0
11
3
0
3
3
0
10
2
0
2
2
0
MMC2107 – Rev. 2.0
1
9
0
1
1
0
MOTOROLA
Bit 0
Bit 8
Bit 0
Bit 0
0
0