MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 564

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

JTAG Test Access Port and OnCE
21.14.4.2 OnCE Control Register
Technical Data
564
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
The 32-bit OnCE control register (OCR) selects the events that put the
device in debug mode and enables or disables sections of the OnCE
logic.
SQC1 and SQC0 — Sequential Control Field
The SQC field allows memory breakpoint B and trace occurrences to
be suspended until a qualifying event occurs. Test logic reset clears
the SQC field. See
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 31
Bit 23
Bit 15
BCB1
Bit 7
DR
0
0
0
0
0
0
JTAG Test Access Port and OnCE
Figure 21-9. OnCE Control Register (OCR)
Go to: www.freescale.com
= Unimplemented or reserved
BCB0
IDRE
30
22
14
0
0
0
0
0
6
0
Table
TME
RCA
29
21
13
0
0
0
0
0
5
0
21-5.
FRZC
BCA4
28
20
12
0
0
0
0
0
4
0
BCA3
RCB
27
19
11
0
0
0
0
0
3
0
BCB4
BCA2
26
18
10
0
0
0
0
0
2
0
MMC2107 – Rev. 2.0
SQC1
BCB3
BCA1
25
17
0
0
0
9
0
1
0
MOTOROLA
SQC0
BCB2
BCA0
Bit 24
Bit 16
Bit 8
Bit 0
0
0
0
0
0