MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 274

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
Watchdog Timer Module
13.6 Memory Map and Registers
13.6.1 Memory Map
13.6.2 Registers
Technical Data
274
This subsection describes the memory map and registers for the
watchdog timer. The watchdog timer has a base address of
0x00c7_0000.
Refer to
The watchdog timer programming model consists of these registers:
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User
0x00c7_0000
0x00c7_0002
0x00c7_0004
0x00c7_0006
Freescale Semiconductor, Inc.
mode accesses to supervisor only addresses have no effect and result in a cycle
termination transfer error.
Address
For More Information On This Product,
The watchdog control register (WCR) configures watchdog timer
operation.
The watchdog modulus register (WMR) determines the timer
modulus reload value.
The watchdog count register (WCNTR) provides visibility to the
watchdog counter value.
The watchdog service register (WSR) requires a service
sequence to prevent reset.
Table 13-1
Table 13-1. Watchdog Timer Module Memory Map
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Watchdog Timer Module
for an overview of the watchdog memory map.
Bits 15–8
Watchdog modulus register (WMR)
Watchdog count register (WCNTR)
Watchdog service register (WSR)
Watchdog control register (WCR)
Bits 7–0
MMC2107 – Rev. 2.0
MOTOROLA
Access
S/U
S/U
S
S
(1)