MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 411

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

18.8 Register Descriptions
18.8.1 QADC Module Configuration Register
MMC2107 – Rev. 2.0
MOTOROLA
Address: 0x00ca_0000 and 0x00ca_0001
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 18-3. QADC Module Configuration Register (QADCMCR)
This subsection describes the QADC registers.
The QADCMCR contains fields and bits that control freeze and stop
modes and determines the privilege level required to access most
registers.
QSTOP — Stop Enable Bit
QDBG — Debug Enable Bit
SUPV — Supervisor/Unrestricted Data Space Bit
Freescale Semiconductor, Inc.
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Queued Analog-to-Digital Converter (QADC)
QSTOP
1 = Forces QADC to idle state
0 = QADC is not forced to idle state
1 = Finish any conversion in progress, then freezes in debug mode
0 = Ignore request to enter debug mode and continue conversions
1 = Only supervisor mode access allowed; user mode accesses
0 = Supervisor and user mode accesses allowed
SUPV
Bit 15
Bit 7
0
1
have no effect and result in a cycle termination transfer error
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= Writes have no effect and the access terminates without a transfer error exception.
QDBG
14
0
6
0
0
13
0
0
5
0
0
12
0
0
4
0
0
Queued Analog-to-Digital Converter (QADC)
11
0
0
3
0
0
10
0
0
2
0
0
Register Descriptions
9
0
0
1
0
0
Technical Data
Bit 8
Bit 0
0
0
0
0
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