MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 405

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

18.5.2 Stop Mode
18.6 Signals
MMC2107 – Rev. 2.0
MOTOROLA
The QADC enters a low-power idle state whenever the QSTOP bit is set
or the part is in stop mode.
QADC stop:
Because the bias currents to the analog circuit are turned off in stop, the
QADC requires some recovery time (t
The QADC uses the external pins shown in
channel/port pins that can support up to 18 channels when external
multiplexing is used (including internal channels). All of the channel pins
can also be used as general-purpose digital port pins. In addition, there
are also two analog reference pins and two analog submodule power
pins.
The QADC has external trigger inputs and the multiplexer outputs
combined onto some of the channel pins.
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Freescale Semiconductor, Inc.
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Queued Analog-to-Digital Converter (QADC)
Disables the analog-to-digital converter, effectively turning off the
analog circuit.
Aborts the conversion sequence in progress
Changes the data direction register (DDRQA), port data registers
(PORTQA and PORTQB), control registers (QACR2, QACR1, and
QACR0) and the status registers (QASR1 and QASR0) to
read-only. Only the module configuration register (QADCMCR) is
writable.
Causes the RAM to not be accessible, can not read valid results
from RAM (result word table and CCW) nor write to the RAM
(result word table and CCW).
Resets QACR1, QACR2, QASR0, and QASR1
Holds the QADC periodic/interval timer in reset
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Queued Analog-to-Digital Converter (QADC)
SR
) to stabilize the analog circuits.
Figure
18-2. There are eight
Technical Data
Signals
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