MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 150

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

M•CORE M210 Central Processor Unit (CPU)
6.7 Operand Addressing Capabilities
6.8 Instruction Set Overview
Technical Data
150
M•CORE accesses all memory operands through load and store
instructions, transferring data between the general-purpose registers
and memory. Register-plus-four-bit scaled displacement addressing
mode is used for load and store instructions addressing byte, half-word,
and word data.
Load and store multiple instructions allow a subset of the 16
general-purpose registers to be transferred to or from a base address
pointed to by register R0 (the default stack pointer by convention).
Load and store register quadrant instructions use register indirect
addressing to transfer a register quadrant to or from memory.
The instruction set is tailored to support high-level languages and is
optimized for those instructions most commonly executed. A standard
set of arithmetic and logical instructions is provided, as well as
instruction support for bit operations, byte extraction, data movement,
control flow modification, and a small set of conditionally executed
instructions which can be useful in eliminating short conditional
branches.
Table 6-1
to the M•CORE Reference Manual (Motorola document order number
MCORERM/AD) for more details on instruction operation.
ABS
ADDC
ADDI
ADDU
AND
ANDI
ANDN
ASR
ASRC
Mnemonic
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
Table 6-1. M•CORE Instruction Set (Sheet 1 of 3)
is an alphabetized listing of the M•CORE instruction set. Refer
Go to: www.freescale.com
Absolute Value
Add with C Bit
Add Immediate
Add Unsigned
Logical AND
Logical AND Immediate
AND NOT
Arithmetic Shift Right
Arithmetic Shift Right, Update C Bit
Description
MMC2107 – Rev. 2.0
MOTOROLA