MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 172

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Interrupt Controller Module
7.8.4.3 Interrupt Source Configuration
7.8.5 Interrupts
Technical Data
172
Source Module
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
ADC
SCI1
SCI2
SPI
MODF Mode fault
TDRE
RDRF
TDRE
RDRF
SPIF
IDLE
IDLE
PF1
CF1
PF2
CF2
Flag
OR
OR
TC
TC
Each module that is capable of generating an interrupt request has an
interrupt request enable/disable bit. To allow the interrupt source to be
asserted, set the local interrupt enable bit.
Once an interrupt request is asserted, the module keeps the source
asserted until the interrupt service routine performs a special sequence
to clear the interrupt flag. Clearing the flag negates the interrupt request.
The interrupt controller assigns a number to each interrupt source, as
Table 7-6
Transmit data register empty
Receive data register full
Transmit data register empty
Receive data register full
Queue 1 conversion pause
Queue 1 conversion complete Write CF1 = 0 after reading CF1 = 1
Queue 2 conversion pause
Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1
Transfer complete
Transmit complete
Receiver overrun
Receiver line idle
Transmit complete
Receiver overrun
Receiver line idle
Table 7-6. Interrupt Source Assignment
Freescale Semiconductor, Inc.
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Source Description
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Interrupt Controller Module
Write PF1 = 0 after reading PF1 = 1
Write PF2 = 0 after reading PF2 = 1
Write to SPICR1 after reading MODF = 1
Access SPIDR after reading SPIF = 1
Write SCIDRL after reading TDRE = 1
Write SCIDRL after reading TC = 1
Read SCIDRL after reading RDRF = 1
Read SCIDRL after reading OR = 1
Read SCIDRL after reading IDLE = 1
Write SCIDRL after reading TDRE = 1
Write SCIDRL after reading TC = 1
Read SCIDRL after reading RDRF = 1
Read SCIDRL after reading OR = 1
Read SCIDRL after reading IDLE = 1
Flag Clearing Mechanism
MMC2107 – Rev. 2.0
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