MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 33

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
Figure
16-19
16-20
16-21
16-22
16-23
16-24
16-25
16-26
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
Freescale Semiconductor, Inc.
For More Information On This Product,
Start Bit Search Example 3 . . . . . . . . . . . . . . . . . . . . . . . . 360
Start Bit Search Example 4 . . . . . . . . . . . . . . . . . . . . . . . . 361
Start Bit Search Example 5 . . . . . . . . . . . . . . . . . . . . . . . . 361
Start Bit Search Example 6 . . . . . . . . . . . . . . . . . . . . . . . . 362
Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Single-Wire Operation (LOOPS = 1, RSRC = 1) . . . . . . . . 366
Loop Operation (LOOPS = 1, RSRC = 0) . . . . . . . . . . . . . 367
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
SPI Control Register 1 (SPICR1) . . . . . . . . . . . . . . . . . . . . 376
SPI Control Register 2 (SPICR2) . . . . . . . . . . . . . . . . . . . . 378
SPI Baud Rate Register (SPIBR) . . . . . . . . . . . . . . . . . . . . 379
SPI Status Register (SPISR) . . . . . . . . . . . . . . . . . . . . . . .381
SPI Data Register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . 382
SPI Pullup and Reduced Drive Register (SPIPURD) . . . . .383
SPI Port Data Register (SPIPORT) . . . . . . . . . . . . . . . . . .384
SPI Port Data Direction Register (SPIDDR). . . . . . . . . . . . 385
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
SPI Clock Format 1 (CPHA = 1). . . . . . . . . . . . . . . . . . . . . 389
SPI Clock Format 0 (CPHA = 0). . . . . . . . . . . . . . . . . . . . . 391
Transmission Error Due to Master/Slave Clock Skew . . . .392
QADC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
QADC Input and Output Signals . . . . . . . . . . . . . . . . . . . . 406
QADC Module Configuration Register (QADCMCR) . . . . .411
QADC Test Register (QADCTEST) . . . . . . . . . . . . . . . . . .412
QADC Port QA Data Register (PORTQA) . . . . . . . . . . . . . 413
QADC Port QB Data Register (PORTQB) . . . . . . . . . . . . . 413
QADC Port QA Data Direction Register (DDRQA). . . . . . . 415
QADC Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . 416
QADC Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . 419
QADC Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . 422
QADC Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . .427
Queue Status Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . 435
QADC Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . .436
Go to: www.freescale.com
List of Figures
Title
Technical Data
List of Figures
Page
33