MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 48

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

General Description
1.4 Block Diagram
Technical Data
48
The basic structure of the MMC2107 is shown in
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Freescale Semiconductor, Inc.
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General-purpose input/output (GPIO):
– Up to 72 bits of GPIO
– Coherent 32-bit control
– Bit manipulation supported via set/clear functions
– Unused peripheral pins may be used as extra GPIO.
– Reduced drive control
M•CORE to IPbus interface:
– Complete interfacing between the M•CORE bus and the IPbus
– Minimum of three clocks for peripheral bus access
– Data alignment and data width conversion between the
External interface:
– Provides for direct support of asynchronous random-access
– Support interfacing to 16-bit and 32-bit data buses
– 32-bit external bidirectional data bus
– 23-bit address bus
– Four chip selects
– Byte/write enables
– Ability to boot from internal or external memories
– Internal bus activity is visible via show-cycle mode
– Special chip selects support replacement of GPIO with
– Emulation of internal page mode FLASH support
Joint Test Action Group (JTAG) support for system-level board
testing
peripheral bus
M•CORE 32-bit data bus and the IPbus peripheral data buses
memory (RAM), read-only memory (ROM), and FLASH
external logic (port replacement logic)
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General Description
Figure
MMC2107 – Rev. 2.0
1-1.
MOTOROLA