MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 500

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

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Queued Analog-to-Digital Converter (QADC)
18.12 Interrupts
18.12.1 Interrupt Operation
Technical Data
500
The four interrupt lines are outputs of the module and have no priority or
arbitration within the module.
QADC inputs can be monitored by polling or by using interrupts. When
interrupts are not needed, software can disable the pause and
completion interrupts and monitor the completion flag and the pause flag
for each queue in the status register (QASR). In other words, flag bits
can be polled to determine when new results are available.
Table 18-18
correspond to queue 1 and queue 2 activity.
If interrupts are enabled for an event, the QADC requests interrupt
service when the event occurs. Using interrupts does not require
continuously polling the status flags to see if an event has taken place.
Queue 1
Queue 2
Queue
Source Impedance
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Queued Analog-to-Digital Converter (QADC)
Table 18-18. QADC Status Flags and Interrupt Sources
Table 18-17. Error Resulting From Input Leakage (I
100 k
10 k
1 k
Result written to last CCW in queue 1
Result written for a CCW with pause bit set in
Result written to last CCW in queue 2
Result written for a CCW with pause bit set in
queue 1
queue 2
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shows the status flag and interrupt enable bits which
0.2 counts
Queue Activity
2 counts
100 nA
—
Leakage Value (10-Bit Conversions)
0.4 counts
200 nA
4 count
—
0.1 counts
10 counts
1 counts
500 nA
Status
MMC2107 – Rev. 2.0
Flag
CF1
CF2
PF1
PF2
MOTOROLA
0.2 counts
Off
20 counts
Enable Bit
1000 nA
2 counts
Interrupt
CIE1
CIE2
PIE1
PIE2
)