MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 570

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

JTAG Test Access Port and OnCE
21.14.5 OnCE Decoder (ODEC)
21.14.6 Memory Breakpoint Logic
Technical Data
570
The ODEC receives as input the 8-bit command from the OCMR and
status signals from the processor. The ODEC generates all the strobes
required for reading and writing the selected OnCE registers.
Memory breakpoints can be set for a particular memory location or on
accesses within an address range. The breakpoint logic contains an
input latch for addresses, registers that store the base address and
address mask, comparators, attribute qualifiers, and a breakpoint
counter.
memory breakpoint logic. This logic is duplicated to provide two
independent breakpoint resources.
DSO
Freescale Semiconductor, Inc.
DSCK
For More Information On This Product,
Figure 21-11
DSI
JTAG Test Access Port and OnCE
Figure 21-11. OnCE Memory Breakpoint Logic
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ADDRESS MASK REGISTER X
ADDRESS BASE REGISTER X
MEMORY ADDRESS LATCH
ADDRESS COMPARATOR
BREAKPOINT COUNTER
illustrates the basic functionality of the OnCE
ADDR[31:0]
COUNT = 0
MATCH
DEC
MMC2107 – Rev. 2.0
ATTR
QUALIFICATION
BREAKPOINT
ISBKPTx
MEMORY
MOTOROLA
BC[4:0], RCx
BREAKPOINT
MATCH
OCCURRED