MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 479

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
CLOCK (f
EXAMPLE 1
EXAMPLE 2
SYSTEM
QCLK
QCLK
sys
)
NOTE:
Figure 18-43. QADC Clock Programmability Examples
Figure 18-43
programmability. The examples include conversion times based on this
assumption:
Figure 18-43
for a single conversion in a queue. For other MCU system clock
frequencies and other input sample times, the same calculations can be
made.
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
The MCU system clock frequency is the basis of the QADC timing. The
QADC requires that the system clock frequency be at least twice the
QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH
field selects the number of system clock cycles in the high phase of the
QCLK wave. The 3-bit PSL field selects the number of system clock
cycles in the low phase of the QCLK wave.
Example Number
Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Control Register 0 Information
1
2
Go to: www.freescale.com
Table 18-15. QADC Clock Programmability
and
and
Table 18-15
Table 18-15
Frequency
40 MHz
32 MHz
20 CYCLES
also show the conversion time calculated
show examples of QCLK
PSH
Queued Analog-to-Digital Converter (QADC)
11
7
PSL
7
7
QCLK
(MHz)
2.0
2.0
Input Sample Time
IST = Binary 00
Conversion Time
Technical Data
Digital Control
( s)
7.0
7.0
479