MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 35

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
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Freescale Semiconductor, Inc.
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Gated Mode, Continuous Scan Timing . . . . . . . . . . . . . . . 491
Star-Ground at the Point of Power Supply Origin. . . . . . . . 493
Input Pin Subjected to Negative Stress . . . . . . . . . . . . . . . 494
Input Pin Subjected to Positive Stress . . . . . . . . . . . . . . . . 494
External Multiplexing of Analog Signal Sources. . . . . . . . .496
Electrical Model of an A/D Input Pin. . . . . . . . . . . . . . . . . . 497
Read Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
Write Cycle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Master Mode — 1-Clock Read and Write Cycle. . . . . . . . .515
Master Mode — 2-Clock Read and Write Cycle. . . . . . . . .515
Internal (Show) Cycle Followed . . . . . . . . . . . . . . . . . . . . . . . .
Internal (Show) Cycle Followed
Chip Select Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 523
Chip Select Control Register 0 (CSCR0) . . . . . . . . . . . . . .525
Chip Select Control Register 1 (CSCR1) . . . . . . . . . . . . . .526
Chip Select Control Register 2 (CSCR2) . . . . . . . . . . . . . .526
Chip Select Control Register 3 (CSCR3) . . . . . . . . . . . . . .527
Top-Level Tap Module and Low-Level (OnCE)
Top-Level TAP Controller State Machine . . . . . . . . . . . . . .540
IDCODE Register Bit Specification . . . . . . . . . . . . . . . . . .545
OnCE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Low-Level (OnCE) Tap Module Data Registers (DRs). . . . 554
OnCE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
OnCE Controller and Serial Interface. . . . . . . . . . . . . . . . . 559
OnCE Command Register (OCMR) . . . . . . . . . . . . . . . . . . 562
OnCE Control Register (OCR) . . . . . . . . . . . . . . . . . . . . . . 564
OnCE Status Register (OSR) . . . . . . . . . . . . . . . . . . . . . . .568
OnCE Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . 570
OnCE Trace Logic Block Diagram . . . . . . . . . . . . . . . . . . .573
CPU Scan Chain Register (CPUSCR) . . . . . . . . . . . . . . . . 576
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by External 1-Clock Read . . . . . . . . . . . . . . . . . . . . . . .518
by External 1-Clock Write . . . . . . . . . . . . . . . . . . . . . . .519
TAP Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
List of Figures
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Technical Data
List of Figures
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