MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 197

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
EHV
HVS
Recovery = 48 scaled clocks or 128 clocks
NOTE:
RECOVERY
SCLKR[2:0] — System Clock Range Field
The SCLKR[2:0] bits are not write protected by the SES bit. Unless the
PAWS[2] bit is set, writes to SCLKR[2:0] in software should not be
changed if SES = 1.
To control the pulse widths for program and erase operations, the CMFR
uses the system clock and the timing control in CMFRCTL. The total
pulse time is defined by:
Where:
The recovery time is the time that the CMFR requires to remove the
program or erase voltage from the array before switching to another
mode of operation. The recovery time is determined by the
SCLKR[2:0] field and the ERASE bit. If SCLKR is not 000, the
recovery time is 48 of the scaled clock periods. If SCLKR = 000 the
recovery time is 128 clocks.
Once reset is completed HVS indicates no program or erase pulse
(HVS = 0).
The read/write SCLKR[2:0] field selects the system clock range for
program/erase pulse timing.
R = clock scaling (see
N = 5 + CLKPE[1:0] + ( (ERASE)
M = 1 + CLKPM[6:0]
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9-6. Pulse Status Timing
Non-Volatile Memory FLASH (CMFR)
pulse width = system clock period
Go to: www.freescale.com
Table
PULSE WIDTH
9-4)
10)
Non-Volatile Memory FLASH (CMFR)
R
Registers and Memory Map
2
RECOVERY
N
M
Technical Data
197