MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 307

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

15.7.8 Timer Control Register 1
MMC2107 – Rev. 2.0
MOTOROLA
Address: TIM1 — 0x00ce_0009
Reset:
Read: Anytime
Write: Anytime
OMx/OLx — Output Mode/Output Level Bits
Read:
Write:
These bit pairs select the output action to be taken as a result of a
successful output compare. When either OMx or OLx is set and the
IOSx bit is set, the pin is an output regardless of the state of the
corresponding DDR bit.
Channel 3 shares a pin with the pulse accumulator input pin. To use
the PAI input, clear both the OM3 and OL3 bits and clear the OC3M3
bit in the output compare 3 mask register.
Freescale Semiconductor, Inc.
For More Information On This Product,
TIM2 — 0x00cf_0009
OM3
Bit 7
Figure 15-11. Timer Control Register 1 (TIMCTL1)
OMx:OLx
0
Timer Modules (TIM1 and TIM2)
Table 15-3. Output Compare Action Selection
00
01
10
11
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= Writes have no effect and the access terminates without a transfer error exception.
OL3
6
0
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line
Set OCx line
OM2
5
0
Action on Output Compare
OL2
4
0
OM1
3
0
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
OL1
2
0
OM0
1
0
Technical Data
Bit 0
OL0
0
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