MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 478

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Queued Analog-to-Digital Converter (QADC)
Technical Data
478
NOTE:
The guideline for selecting PSH and PSL is to maintain approximately
50 percent duty cycle; for prescaler values less than 16 or PSH ~=PSL.
For prescaler values greater than 16, keep PSL as large as possible.
Figure 18-42
width signal generator. A 5-bit down counter, clocked at the system clock
rate, is used to create both the high phase and the low phase of the
QCLK signal. At the beginning of the high phase, the 5-bit counter is
loaded with the 5-bit PSH value. When the 0 detector finds that the high
phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s
complement match with the 3-bit PSL value, which is the end of the low
phase of the QCLK.
These equations define QCLK frequency:
Where:
These are equations for calculating the QCLK high and low phases in
example 1:
These are equations for calculating the QCLK high and low phases in
example 2:
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
f
f
sys
QCLK
= system clock frequency
f
high QCLK time = (11 + 1) ÷ 40
= QCLK frequency
Go to: www.freescale.com
QCLK
high QCLK time = (7 + 1) ÷ 32
low QCLK time = (7 + 1) ÷ 40
low QCLK time = (7 + 1) ÷ 32
shows that the prescaler is essentially a variable pulse
= 1 ÷ (high QCLK time + low QCLK time)
high QCLK time = (PSH + 1) ÷ f
low QCLK time = (PSL + 1) ÷ f
f
f
QCLK
QCLK
= 1/(300 + 200) = 2 MHz
= 1/(250 + 250) = 2 MHz
10
10
10
10
6
6
6
6
= 200 ns
= 250 ns
sys
= 250 ns
sys
= 300 ns
MMC2107 – Rev. 2.0
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