MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 538

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

JTAG Test Access Port and OnCE
21.3.1 Test Clock (TCLK)
21.3.2 Test Mode Select (TMS)
21.3.3 Test Data Input (TDI)
21.3.4 Test Data Output (TDO)
21.3.5 Test Reset (TRST)
21.3.6 Debug Event (DE)
Technical Data
538
TCLK is a test clock input to synchronize the test logic. TCLK is
independent of the MMC2107 processor clock. It includes an internal
pullup resistor.
TMS is a test mode select input (with an internal pullup resistor) that is
sampled on the rising edge of TCLK to sequence the TAP controller’s
state machine.
TDI is a serial test data input (with an internal pullup resistor) that is
sampled on the rising edge of TCLK.
TDO is a three-state test data output that is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of
TCLK.
TRST is an active low asynchronous reset with an internal pullup resistor
that forces the TAP controller into the test-logic-reset state.
This is a bidirectional, active-low signal.
As an output, this signal will be asserted for three system clocks,
synchronous to the rising CLKOUT edge, to acknowledge that the CPU
has entered debug mode as a result of a debug request or a breakpoint
condition.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA