MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 297

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

15.5 Modes of Operation
15.5.1 Supervisor and User Modes
15.5.2 Run Mode
15.5.3 Stop Mode
15.5.4 Wait, Doze, and Debug Modes
15.5.5 Test Mode
MMC2107 – Rev. 2.0
MOTOROLA
This subsection describes the supervisor and user modes, the five
low-power options, and test mode.
The SO bit in the chip-select control register determines whether the
processor is operating in user mode or supervisor mode. Accessing
supervisor address locations while not in supervisor mode causes the
timer to assert a transfer error.
Clearing the TIMEN bit in the timer system control register 1 (TIMSCR1)
or the PAE bit in the pulse accumulator control register (TIMPACTL)
reduces power consumption in run mode. Timer registers are still
accessible, but all timer functions are disabled.
If the central processor unit (CPU) enters stop mode, timer operation
stops. Upon exiting stop mode, the timer resumes operation unless stop
mode was exited by reset.
The timer is unaffected by these low-power modes.
A high signal on the TEST pin puts the processor in test mode or special
mode. The timer behaves as in user mode, except that timer test
registers are accessible.
Freescale Semiconductor, Inc.
For More Information On This Product,
Timer Modules (TIM1 and TIM2)
Go to: www.freescale.com
Timer Modules (TIM1 and TIM2)
Modes of Operation
Technical Data
297