MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 284

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Programmable Interrupt Timer Modules (PIT1 and PIT2)
14.6 Memory Map and Registers
14.6.1 Memory Map
14.6.2 Registers
Technical Data
284
0x00c8_0000
0x00c8_0002
0x00c8_0004
0x00c8_0006
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
Address
only addresses have no effect and result in a cycle termination transfer error.
PIT1
Table 14-1. Programmable Interrupt Timer Modules Memory Map
0x00c9_0000
0x00c9_0002
0x00c9_0004
0x00c9_0006
Address
PIT2
This subsection describes the memory map and register structure for
PIT1 and PIT2.
Refer to
This device has two programmable interrupt timers. PIT1 has a base
address located at 0x00c8_0000. PIT2 base address is 0x00c9_0000.
The PIT programming model consists of these registers:
Programmable Interrupt Timer Modules (PIT1 and PIT2)
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•
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Freescale Semiconductor, Inc.
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The PIT control and status register (PCSR) configures the timer’s
operation.
The PIT modulus register (PMR) determines the timer modulus
reload value.
The PIT count register (PCNTR) provides visibility to the counter
value.
Table 14-1
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PIT control and status register (PCSR)
Bits 15–8
for a description of the memory map.
PIT modulus register (PMR)
PIT count register (PCNTR)
Unimplemented
(2)
Bits 7–0
MMC2107 – Rev. 2.0
MOTOROLA
Access
S/U
—
S
S
(1)