MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 72

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
System Memory Map
Technical Data
72
Programmable Interrupt Timer 1 (PIT1) and Programming Interrupt Timer 2 (PIT2)
Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####.
P = Current pin state
0x00c7_0006
0x00c7_0007
0x00c7_0008
0x00c8_0000
0x00c8_0001
0x00c9_0000
0x00c9_0001
0x00c8_0002
0x00c8_0003
0x00c9_0002
0x00c9_0003
0x00c7_ffff
Address
PIT Control and Status
PIT Modulus Register
Register Name
Watchdog Service
Register (PCSR)
U = Unaffected
Register (WSR)
Unimplemented
See page 279.
See page 285.
See page 288.
Figure 2-2. Register Summary (Sheet 19 of 34)
(PMR)
Freescale Semiconductor, Inc.
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Bit 15
WS15
Bit 15
Bit 15
PM15
WS7
Bit 7
Bit 7
Bit 7
Bit 7
PM7
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0
0
0
0
0
0
1
1
Access results in a bus monitor timeout generating an access termination transfer error.
System Memory Map
= Writes have no effect and the access terminates without a transfer error exception.
PDOZE
WS14
PM14
WS6
PM6
14
14
14
0
6
0
6
0
0
6
0
1
6
1
PDBG
WS13
PM13
WS5
PM5
13
13
13
0
5
0
5
0
0
5
0
1
5
1
WS12
PM12
OVW
WS4
PM4
12
12
12
0
4
0
4
0
0
4
0
1
4
1
Bit Number
WS11
PRE3
PM11
WS3
PM3
PIE
11
11
11
0
3
0
3
0
3
0
1
3
1
WS10
PRE2
PM10
WS2
PM2
PIF
10
10
10
0
2
0
2
0
2
0
1
2
1
MMC2107 – Rev. 2.0
PRE1
WS9
WS1
RLD
PM9
PM1
0
1
0
1
0
1
0
1
1
1
9
9
9
MOTOROLA
PRE0
WS8
WS0
Bit 8
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
PM8
Bit 0
PM0
EN
0
0
0
0
1
1